1. Field of the Invention
The present invention relates to a static semiconductor memory device and a method of controlling the same.
2. Description of the Related Art
A typical conventional static semiconductor memory device is an SRAM (Static Random Access Memory). FIG. 3 is a view showing the memory cell array of a conventional SRAM. As shown in FIG. 3, n memory cells CELL0, CELL1, . . . , CELLn (to be referred to as memory cells CELL hereinafter) are connected to a pair of bit lines BL and XBL. Each of the bit lines BL and XBL is connected to a power supply voltage (Vdd) through a precharge p-MOSFET 51. The signal line of a precharge cancel signal φ is connected to the gate terminals of the p-MOSFETs 51 so that the p-MOSFETs 51 are ON/OFF-controlled by the precharge cancel signal φ. Note that the bit lines BL and XBL have a complementary relationship.
Each memory cell CELL is formed from six transistors. Four of them, i.e., two p-MOSFETs 52a and two n-MOSFETs 52b construct a data latch circuit that holds data. Two remaining n-MOSFETs 53 control connection between the data latch circuit and the bit lines BL and XBL. Word lines WL0, WL1, . . . , WLn are connected to the gate terminals of the n-MOSFETs 53 that control connection to the bit lines BL and XBL. The n-MOSFETs 53 are ON/OFF-controlled by the signal of the word line WL. The above-described SRAM has a standby mode, write mode, and read mode. In the standby mode, the memory cell is neither write- nor read-accessed.
The arrangement of the above-described data latch circuit will be described in detail. The two p-MOSFETs 52a are respectively connected between nodes A and B and the power supply lines that supply the power supply voltage. The two n-MOSFETs 52b are connected between ground and the nodes A and B, respectively. The gate terminals and drain terminals of the p-MOSFETs 52a and n-MOSFETs 52b are connected to each other to form an inverter. The connection point between the gate terminals and that between the drain terminals (nodes A and B) are also connected. Thus, a data latch circuit is formed.
FIG. 4 is a waveform chart showing the operation of the memory cell array shown in FIG. 3. At time t70, the SRAM is in the read mode. The bit lines BL and XBL are kept at high level because the p-MOSFETs 51 are turned on. At time t71, the precharge cancel signal φ changes to high level to cancel precharge of the bit lines BL and XBL. In synchronism with this operation, the word line WL of the memory cell CELL to be accessed changes to high level to execute read operation (in the read mode). Referring to FIG. 4, a change in potential of the bit lines BL and XBL indicates the read operation.
At time t72, when the read operation is ended, the SRAM changes to the standby mode. The precharge cancel signal φ changes to low level to start precharging the bit lines BL and XBL. In the waveforms of the signals in write operation (in the write mode), only the change in potential of the bit lines BL and XBL is different from that in the waveforms of the signals in the above-described read operation.
In the above-described SRAM, since the bit lines BL and XBL are held at high level during the standby mode, a leakage current from the bit line BL or XBL to the memory cell CELL is generated.
For example, assume that the node A on the right side of the data latch circuit in the memory cell CELL0 shown in FIG. 3 holds low level. The node A is connected to the bit line XBL through the transistor 53. During the standby mode, the bit line XBL is precharged to high level. Hence, a leakage current Ioff flows from the bit line XBL to the node A. At the node B on the left side, since the two terminals (source and drain terminals) of the transistor 53 are at high level, no leakage current flows. In addition, as indicated by the memory cell CELLn, while the node B holds low level, the leakage current Ioff flows from the bit line BL to the node B.
As described above, the leakage current Ioff flows to the bit line BL or XBL in accordance with the data held by all the memory cells CELL. That is, in FIG. 3, since the n memory cells CELL are connected to the bit lines BL and XBL, a total leakage current Ioff×n flows to the bit line BL or XBL. When the above SRAM is used in a device such as a cellular phone with a very long standby time, the bit lines BL and XBL are always precharged to high level, and the leakage current continuously flows.
To reduce the leakage current of the memory cell CELL in the standby mode in the above-described SRAM, the bit lines BL and XBL are set in a floating state. FIG. 5 is a waveform chart when the method of setting the bit lines BL and XBL in the floating state is employed in the standby mode of the SRAM shown in FIG. 3. In this method, at time t80, the SRAM is in the read mode and in the non-access state for the memory cell CELL. Hence, the precharge cancel signal φ is changed to high level to set the bit lines BL and XBL in the floating state.
Next, at time t81, before accessing the memory cell CELL, the precharge cancel signal φ is changed to low level to precharge the bit lines BL and XBL. The timing to change the precharge cancel signal φ to low level corresponds to the trailing edge (or leading edge) of the clock signal, as shown in FIG. 5.
At time t82, the precharge cancel signal φ is changed to high level, and simultaneously, the word line WL is changed to high level to access the memory cell CELL. As described above, even during the read mode, the bit lines BL and XBL are set in the floating state in the non-access state for the memory cell CELL, thereby reducing the leakage current. In the access state, the bit lines BL and XBL are precharged before accessing the memory cell CELL. Then, the memory cell CELL is accessed.
At time t83, the SRAM is set in the standby mode. The word line WL is changed to low level, and the bit lines BL and XBL are set in the floating state. A time Ta from time t81 to t82 shown in FIG. 5 is necessary for precharging the bit lines BL and XBL. As shown in FIG. 5, the word line WL changes to high level with a delay corresponding to the time Ta from the trailing edge of the clock signal. The precharge cancel signal φ maintains low level for the time Ta and then changes to high level.
As described above, when the bit lines BL and XBL are in the floating state and have an arbitrary potential, the following leakage currents flow between the bit lines BL and XBL and the memory cell CELL: a leakage current Ioff—L (VBL) flowing from the bit lines BL and XBL to the above-described node A or B that has a lower potential (to be referred to as a low node hereinafter) and a leakage current Ioff—H (VBL) flowing from the above-described node A or B that has a higher potential (to be referred to as a high node hereinafter) to the bit lines BL and XBL. FIG. 6 shows the dependence between these leakage currents and the potential of the bit lines BL and XBL (VBL indicates the potential of the bit lines BL and XBL).
As shown in FIG. 6, the leakage current Ioff—L (VBL) that flows from the bit lines BL and XBL to the low node becomes small as the VBL becomes low. Conversely, the leakage current flows from the high node to the bit lines BL and XBL becomes small as the VBL becomes high. When the bit lines BL and XBL are set in the floating state, the potential of the bit lines BL and XBL stabilizes at the potential VBL=VBLo that satisfies       Ioff_L    ⁢          (              V        ⁢                                  ⁢        B        ⁢                                  ⁢        L            )        ×          (              number        ⁢                                  ⁢        of        ⁢                                  ⁢                  “          L          ”                ⁢                                  ⁢        nodes        ⁢                                  ⁢        connected        ⁢                                  ⁢        to        ⁢                                  ⁢        bit        ⁢                                  ⁢        line        ⁢                                  ⁢        BL            )        =      Ioff_H    ⁢          (              V        ⁢                                  ⁢        B        ⁢                                  ⁢        L            )        ×                  (                  number          ⁢                                          ⁢          of          ⁢                                          ⁢                      “            H            ”                    ⁢                                          ⁢          nodes          ⁢                                          ⁢          connected          ⁢                                          ⁢          to          ⁢                                          ⁢          bit          ⁢                                          ⁢          line          ⁢                                          ⁢          B          ⁢                                          ⁢          L                )            .      
When m memory cells of the n memory cells CELL connected to a given bit line are high nodes, and (n−m) memory cells are low nodes, the leakage current is given by
m×Ioff—L (VBLo)+(n−m)×Ioff—L (VXBLo) This is the minimum value. That is, when the bit lines BL and XBL are set in the floating state, the potential of the bit lines BL and XBL stabilizes in a state wherein the leakage current is minimized in accordance with the data held by the memory cell CELL.
In the above-described method of reducing the leakage current, the precharge cancel signal φ that sets the bit lines BL and XBL in the floating state and the select signal of the word line WL are generated on the basis of a clock signal. More specifically, in accordance with a change in clock signal, the precharge cancel signal φ is changed to low level to precharge the bit lines BL and XBL at the time t81, and then, the word line WL is changed to high level at the time t82. However, the time required to precharge the bit lines BL and XBL from the time t81 to t82 impedes an increase in access speed.